Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
US9424900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Oct 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking bit line (TBL) and/or a clock signal (e.g., GCLKB)) transitions from one voltage level to another voltage level. A process-and-temperature-dependent bias circuit is provided to control the charge-injection pull-up transistor. The bias circuit causes the charge-injection pull-up transistor to adjust the discharge rate or transition rate of the signal line to compensate for timing delays caused by process or temperature variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.