Patent · US Active

Memory controller and associated method for generating memory address

US9424902B2 · kind B2 · utility

1Cited by

0References

18Claims

0Family size

Assignee

MSTAR SEMICONDUCTOR, INC. · TW

Inventors

Chung-Ching Chen · New Rochelle, US
Chen-Nan Lin · Taipei, TW
Yung Chang · Hsinchu, TW

Key dates

Filing date	Mar 28, 2014
Grant date	Aug 23, 2016
Priority date	—
Expiry date	Nov 12, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.