Non-volatile semiconductor memory device having depletion-type and enhancement-type channel regions
US9424924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device is proposed that has an unprecedented novel structure in which carriers can be injected into a floating gate by applying various voltages of the same polarity. According to the non-volatile semiconductor memory device of the present invention, in a memory transistor, a PN junction is formed at the boundary between a channel region and an opposite polarity type impurity diffusion layer, to allow a floating gate to be charged to have the same polarity as the polarity of the channel region, whereby a part of electrons accelerated in a depletion layer between the channel region and an opposite polarity type extension region, and secondary electrons generated by the accelerated electrons can be injected into the floating gate by being attracted to a gate electrode, as a result of which electrons can be injected into the floating gate even when, without simultaneously applying positive and negative voltages as in the conventional case, various voltages of the same polarity are applied to the floating gate, an impurity diffusion layer, and the opposite polarity type impurity diffusion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.