Method and apparatus for manufacturing three-dimensional-structure memory device
US9425057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2011 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Feb 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and the step for laminating the sacrificial layer includes a step for depositing a second silicon oxide film by supplying dichlorosilane (SiCl2H2) to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.