Sidewall passivation for HEMT devices
US9425301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Sep 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.