Passivated III-V or Ge fin-shaped field effect transistor
US9425314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2014 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Mar 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h′, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.