Coalescing memory transactions
US9430276B2 · kind B2 · utility
9Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0613
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transactional memory system coalesces two outermost transactions in a transactional memory environment. A processor of the transactional memory system executes a first transaction begin instruction of a first outermost transaction and processes the first transaction. Based on encountering a first transaction end instruction of the first outermost transaction, the processor determines whether the first transaction is to-be coalesced with a second outermost transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.