Memory program upon system failure
US9430314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2013 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Apr 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero. Further, the system can include a processing unit configured to provide the timer value to the timer device and the memory address information to the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.