Error correction in memory devices by multiple readings with different references
US9430328B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 15, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Apr 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include memory cells. The method may include receiving a request of reading a selected data word associated with a selected code word stored with an error correction code, and reading a first code word representing a first version of the selected code word by comparing a state of each selected memory cell with a first reference. The method may include verifying the first code word, setting the selected code word according to the first code word in response to a positive verification, reading at least one second code word representing a second version of the selected code word, verifying the second code word, and setting the selected code word according to the second code word in response to a negative verification of the first code word and to a positive verification of the second code word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.