Updating persistent data in persistent memory-based storage
US9430396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Mar 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.