Memory devices and methods of manufacture thereof
US9431107B2 · kind B2 · utility
3Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2012 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Dec 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.