Memory die and method for efficient use of data latches in serving mixed traffic loads
US9431120B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Mar 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory die is provided comprising a non-volatile memory organized in physical pages, a transfer data latch in communication with the non-volatile memory, at least one auxiliary data latch in communication with the transfer data latch, and circuitry. The circuitry is configured to receive a plurality of sense commands, wherein each sense command indicates a physical page in the non-volatile memory to be sensed and a portion of the physical page to be stored in the at least one auxiliary data latch. For each sense command, the circuitry is configured to store data from the physical page sensed by the sense command in the transfer data latch and move data from the portion of the physical page indicated by the sense command to an available location in the at least one auxiliary data latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.