Variable read delay system
US9431129B2 · kind B2 · utility
4Cited by
6References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.