Method for fabricating a multi-gate device
US9431397B2 · kind B2 · utility
1Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Feb 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.