Semiconductor device with vertical memory
US9431415B2 · kind B2 · utility
19Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Nov 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.