Method of producing a III-V fin structure
US9431519B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 22, 2015 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | May 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.