System and method for calibration of a memory interface
US9436387B2 · kind B2 · utility
4Cited by
3References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2014 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Jan 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/388
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. However, in response to an occurrence of a given predetermined interval, the memory interface unit may be configured to calibrate the timing unit using a number of partial calibration segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.