Memory nest efficiency with cache demand generation
US9436608B1 · kind B1 · utility
1Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Mar 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/603
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.