Circuitry for a computing system, LSU arrangement and memory arrangement as well as computing system
US9436624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2013 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Aug 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.