Method and circuits for superclocking
US9436786B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Aug 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and circuits for superclocked operation of a plurality of functionally-equivalent logic circuits are disclosed. One of the plurality of functionally-equivalent logic circuits is selected according to a selection algorithm. In response to selecting one of the plurality of functionally-equivalent logic circuits, superclocked operation of the selected one of the plurality of functionally-equivalent logic circuits is enabled. Superclocked operation of other ones of the plurality of functionally-equivalent logic circuits is disabled. The selected one of the plurality of functionally-equivalent logic circuits is used to process a portion of the input data set at the superclocked clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.