Memory controller and associated signal generating method
US9437262B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 23, 2014 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Mar 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.