Memory operation latency control
US9437264B2 · kind B2 · utility
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2References
17Claims
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Assignee
Inventors
Key dates
| Filing date | Feb 26, 2016 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.