Mechanism for data generation in data processing systems
US9437277B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | May 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.