Patent · US Active

Write address synchronization in 2 read/1write SRAM arrays

US9437285B1 · kind B1 · utility

1Cited by

1References

8Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Harry Barowski · Balingen, DE
Silke Penth · Holzgerlingen, DE
Wolfgang Penth · Holzgerlingen, DE
Tobias Werner · Holzgerlingen, DE

Key dates

Filing date	Mar 15, 2016
Grant date	Sep 6, 2016
Priority date	—
Expiry date	Mar 15, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths provide first and second address data to the at least two address decoders. The first latch is electrically conductive connected to the first data path and the second latch is electrically conductive connected to the second data path. The first latch is further electrically conductive connectable to the second data path via a first multiplexer. The first multiplexer and the at least two latches are configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.