Method for programming non-volatile memory with reduced bit line interference and associated device
US9437319B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Jun 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3486
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.