Shift register circuit for preventing malfunction due to clock skew and memory device including the same
US9437323B2 · kind B2 · utility
1Cited by
1References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Apr 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of latching the output signal of the first latch in synchronization with a second dock having the same skew as the first clock, a second latch capable of latching the output signal of the first flip-flop in synchronization with a third clock having a different skew from the second clock, and a second flip-flop capable of latching the output signal of the second latch circuit in synchronization with a fourth clock having the same skew as the third clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.