Method for forming spacers for a transistor gate
US9437418B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2014 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Nov 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming spacers of a transistor gate having an active layer surmounted by the gate, including forming a porous layer covering the gate and having a dielectric constant equal to or less than that of silicon oxide, forming a protective layer covering the porous layer and the gate, etching the protective layer anisotropically to preserve residual portions of the protective gate only at the flanks of the gate, forming a modified layer by penetration of ions within the porous layer anisotropically to modify the porous layer over its entire thickness above the gate and above the active layer and so as not to modify the entire thickness of the porous layer on the flanks of the gate, the latter being protected by protective spacers constituting porous spacers, and removing the modified layer by etching to leave the protective spacers in place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.