Method for the formation of different gate metal regions of MOS transistors
US9437498B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Mar 3, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Mar 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.