TSV without zero alignment marks
US9437550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2013 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Nov 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor device and method of forming a semiconductor device are disclosed. The method includes providing a substrate. A dielectric layer is formed on the substrate. The dielectric layer includes an upper and lower level. The upper level of the dielectric layer is patterned to form at least first and second trench openings and alignment mark openings. One of the first and second trench openings serve as a through via (TV) trench while another trench opening serves as an interconnect trench. A TV opening aligned to the TV trench is formed. The TV opening extends partially into the substrate. A conductive layer is formed over the substrate to fill the trenches and the openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.