Interconnect structure and method of fabricating same
US9437564B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2013 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Jul 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.