Semiconductor substrate and semiconductor package structure having the same
US9437565B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2014 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Dec 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.