Implementing clock receiver with low jitter and enhanced duty cycle
US9438209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2014 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Dec 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.