Biasing circuit for level shifter with isolation
US9438240B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2015 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.