Apparatus and method for reduced core entry into a power state having a powered down core cache
US9442849B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Dec 29, 2012 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Aug 1, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.