System and method for out-of-order prefetch instructions in an in-order pipeline
US9442861B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2011 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Jun 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, and a method for providing a processor architecture with data prefetching are described. In one embodiment, a system includes one or more processing units that include a first type of in-order pipeline to receive at least one data prefetch instruction. The one or more processing units include a second type of in-order pipeline having issues slots to receive instructions and a data prefetch queue to receive the at least one data prefetch instruction. The data prefetch queue may issue the at least one data prefetch instruction to the second type of in-order pipeline based upon one or more factors (e.g., at least one execution slot of the second type of in-order pipeline being available, priority of the data prefetch instruction).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.