Physical aware technology mapping in synthesis
US9443048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2014 |
| Grant date | Sep 13, 2016 |
| Priority date | — |
| Expiry date | Nov 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.