Circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement

US9448283B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Heiko Ahrens · Munich, DE
• Claudia Latzel · Putzbrunn, DE
• Bernhard Richter · Puchheim, DE

Key dates

• Filing date: Aug 22, 2012
• Grant date: Sep 20, 2016
• Expiry date: Dec 15, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3187
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A circuit arrangement for Logic Built-In Self-Test (LBIST) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. The circuit arrangement includes a second clock division circuitry configured to derive a second punched-out clock. The second punched-out clock has a delay of one or more system clock periods relative to the first punched-out clock. A compacting logic is configured to compact signals received from the scan chains. A sequential retiming element connects the compacting logic to an input circuitry of a MISR. The sequential retiming element is responsive to a trailing edge of the second punched-out clock. The input circuitry is responsive to a leading edge of the second punched-out clock.