Clock domain crossing serial interface
US9448878B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Feb 25, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.