Surface resource view hash for coherent cache operations in texture processing hardware

US9448935B2 · kind B2 · utility

Assignee

• NVIDIA Corporation · US

Inventors

• Jeff Bolz · Austin, US
• Patrick R. Brown · Raleigh, US
• Steven James Heinrich · Huntsville, US
• Dale L. Kirkland · Madison, US
• Joel J. McCormack · Boulder, US

Key dates

• Filing date: Sep 25, 2013
• Grant date: Sep 20, 2016
• Expiry date: Jan 3, 2034

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.