Cache coherence protocol for persistent memories
US9448938B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Jun 9, 2010 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Apr 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having a memory controller, a main memory with at least a portion comprising persistent memory, and at least two processing entities, wherein the memory controller enables the processing entities to access the main memory according to a cache coherence protocol. The cache coherency protocol can signal when the main memory is being updated and when the update has finished. The processing entities can be configured to wait for the main memory to be updated or can access previously stored memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.