Low power hardware algorithms and architectures for spike sorting and detection
US9449225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2005 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | May 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2218/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neuronal recording system featuring a large number of electrodes and a portable wireless front-end integrated circuit for signal processing for low-power spike detection and alignment. The system is configured as a Neuroprocessor and introduces hardware architectures for automatic spike detection and alignment algorithms. The Neuroprocessor can be placed next to the recording electrodes and provide for all stages of spike processing, stimulating neuronal tissues and wireless communications to a host computer. Some of the algorithms are based on principal component analysis (PCA). Others employ a novel Integral Transform. The algorithms execute autonomously, but require off-line training and setting of computational parameters. Pre-recorded neuronal signals evaluate the accuracy of the proposed algorithms and architectures: The recorded data are processed by a standard PCA spike sorting software algorithm, as well as by the several hardware algorithms, and the outcomes are compared.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.