Reducing the number of sequential operations in an application to be performed on a shared memory cell
US9449360B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2011 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Mar 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses to reduce the number of sequential operations such as atomic operations in an application to be performed on a shared memory cell may be provided. A translation unit can detect in the application multiple atomic operations to be performed on the same memory and replaces the multiple atomic operations with an equivalent single atomic operation. In some implementations, the application includes shader code. In some implementations, each of the multiple atomic operations increment a value stored at the same memory by an update amount. The translation unit may calculate the partial prefix sum over all the atomic operations and replace the multiple atomic operations with a single atomic operation to increment the value stored at memory by the sum of the update amounts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.