Memory with bit cell header transistor
US9449656B2 · kind B2 · utility
8Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2013 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a write operation by a header control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.