Memory device
US9449661B2 · kind B2 · utility
8Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Jul 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell electrically connected to a power line and a power supply unit configured to control a voltage level on the power line. The power supply unit receives a control signal corresponding to a write cycle of the memory cell and, responsive to a first state of the control signal, outputs a first voltage level on the power line. Responsive to a second state of the control signal, the power supply unit outputs a second voltage level on the power line, the second voltage level having a magnitude less than a magnitude of the first voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.