Flexible interrupt generation mechanism
US9449714B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 14, 2013 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Jan 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a testing device, a method for implementing efficient interrupt routing. The method includes receiving an interrupt from a plurality of interrupt causes, consulting an interrupt routing table to determine an output interrupt vector, and forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.