Multi-bit MTJ memory cell using two variable resistance layers
US9450021B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Nov 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes a semiconductor memory, and the semiconductor memory includes a variable resistance structure including a material having a resistance that is changed by formation or dissipation of conductive filaments; and a Magnetic Tunnel Junction (MTJ) structure inserted in the variable resistance structure and comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.