Lateral DMOS device with dummy gate
US9450056B2 · kind B2 · utility
8Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2012 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Sep 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.