Method for manufacturing silicon carbide semiconductor device
US9450068B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2013 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Apr 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for manufacturing a silicon carbide semiconductor device having a JFET, a trench is formed in a semiconductor substrate, and a channel layer and a second gate region are formed on an inner wall of the trench. The channel layer and the second gate region are planarized to expose a source region. A first recess deeper than a thickness of the source region is formed on both leading ends of the trench, and an activation annealing process of 1300° C. or higher is conducted in an inert gas atmosphere. A first conductivity type layer formed by the annealing process to cover a corner which is a boundary between a bottom and a side of the first recess is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.