FinFET having superlattice stressor
US9450098B2 · kind B2 · utility
1Cited by
17References
20Claims
0Family size
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Key dates
| Filing date | Feb 19, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Mar 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.