Fabrication methodology for optoelectronic integrated circuits
US9450124B1 · kind B1 · utility
Assignees
Inventor
Key dates
| Filing date | Jun 11, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Jun 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/357
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of forming an integrated circuit employs a plurality of layers supported on a substrate that include i) n-type contact layer, ii) a p-type modulation doped quantum well structure (MDQWS) above the n-type contact layer, iii) n-type MDQWS above the p-type MDQWS, and iv) p-type contact layer(s) above the n-type MDQWS. A feature for a thyristor is defined by a mesa at the p-type contact layer of iv). A first layer of metal is deposited on the feature, which is then etched for at least one other device. Additional layer(s) of metal is deposited on the feature to form cumulative metal layers, which are etched away to form a set of mesas and corresponding electrodes for the thyristor. The cumulative metal layers that cover the feature and contact the mesa at the p-type contact layer of iv) are patterned to form an anode electrode of the thyristor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.